1. Field of the Invention
This invention relates to scan testing functionality for integrated circuits and, more particularly, to inserting scan functionality into a control block of an integrated circuit.
2. Description of the Related Art
Integrated circuits comprise millions of transistors fabricated upon a semiconductor substrate, interconnected by several metal wiring layers placed atop the semiconductor substrate. Manufacturing defects may occur in any of the transistors or in the metal interconnect, causing the integrated circuit not to function properly. Various faults may occur, including stuck-at faults in which a node is stuck at a particular value which is not correct given the state of the integrated circuit; open faults in which an open circuit exists; short faults in which a short circuit exists; etc. To ensure delivery of a quality product to the integrated circuit consumer, designing a high degree of fault testability (or simply "testability") into the integrated circuit is of critical importance.
One method for providing testability in control blocks of an integrated circuit is designing scan test functionality into the control block. Control blocks generally comprise combinatorial logic gates which receive inputs from storage devices and provide outputs to storage devices. The input and output storage devices are clocked with a clock signal which causes the storage devices to periodically capture the value provided to the storage devices. The captured value is provided as an output of the storage device until the next value is captured. Between the periodic captures, the combinatorial logic evaluates and generates new input values. Control blocks embody the control logic which operates data flow elements within the integrated circuit in order to provide the functionality specified for the integrated circuit.
Scan testing involves scanning values into the storage devices of the control block, allowing the combinatorial logic within the control block to evaluate, clocking results of the evaluation into the storage devices, and scanning the results out of the storage devices. Based upon a model of the combinatorial logic design, the expected results for any set of inputs can be determined. If the measured results match the expected results, then the test passes. If the measured results do not match the expected results, the test fails. A set of input patterns (and corresponding expected results) are generated to test for the largest possible number of faults. While generating a set of all possible input patterns would theoretically lead to 100% fault coverage, the number of input patterns would be prohibitive. However, a high degree of test coverage may be achieved by using a much smaller number of patterns. Scan testing effectiveness can be measured as a percentage of all possible faults which are tested by the set of input patterns used. Typically, greater than 95% of the faults tested is required. Often, greater than 99% of the faults can be tested.
In order to scan inputs into the storage devices and scan results out of the storage devices, the storage devices are interconnected in a serial chain (or "scan chain"). One of the storage devices forms the end of the chain, and receives a scan input provided from an input pin to the integrated circuit. Another one of the storage devices forms the other end of the chain, and provides a scan output provided to an output pin of the integrated circuit. The chain of storage devices effectively forms a scan register. The scan register operates as a shift register to allow values to be scanned in and out of the storage devices forming the scan register.
Inserting scan functionality into a control block design involves at least: (i) distributing a scan enable to the storage devices within the control block, the scan enable indicating when scanning of values into or out of the storage devices is being performed; and (ii) connecting the devices together into a scan chain. Unfortunately, inserting scan functionality into a control block design complicates the design process. In addition to iterating the design to meet functional specifications and design requirements, the designer must design the scan functionality. The design must meet timing requirements for the scan enable and scan chain signals, increasing the timing design effort. Additionally, the scan enable and scan chain signals must be routed throughout the control block. Wiring congestion within the control block may be increased, which may impact functional timing. Additionally, placement and routing of logic and storage elements may be impacted by the scan requirements. If logic elements and storage elements which are interconnected are moved farther apart due to scan functionality, functional timing may again be affected. An effective method for inserting scan testing into a control block design is therefore desirable.